1. Field of the Invention
This invention relates to charge coupled devices using single level gates.
2. Description of the Prior Art
Charge coupled devices are generally known and comprise one form of charge transfer device which uses moving potential wells to translate, that is, shift analog charge packets from an input end to an output end of a semiconductor body. The potential wells move in response to changes in potential applied to a series of electrodes or gates formed on an insulating layer applied to the surface of the semiconductor body. Such devices are disclosed in numerous prior art publications and patents, a typical example being U.S. Pat. No. 4,032,952, entitled, "Bulk Charge Transfer Semiconductor Device", issued to S. Ohba et al on Jun. 28, 1977.
From the beginning, the fabrication of charge coupled devices (CCD) has undergone a great deal of development and improvement in performance, with a constant effort being directed to the realization of CCDs with very small pixels for providing high resolution, high quantum efficiency so as to provide increased sensitivity, low noise, and the same clocking voltages for different CCD phases.
The most direct approach is to utilize single level gates with relatively narrow gaps therebetween; however, if the gaps become too wide, the CCD clocking voltages need to be increased in amplitude to compensate for the potential wells or barriers caused by the gaps. Such potential wells or barriers cause loss of CCD transfer efficiency by trapping charge, since the fringing effects of the CCD clocking gates are attenuated with larger gaps.
Typically, the gaps between gates are formed during the CCD gate definition process; however, as the gaps between the gates become increasingly smaller, i.e. in the order of 0.35 .mu.m, defining such narrow gaps becomes increasingly difficult because of resolution limits and projection aligners and limitations in the etching of very narrow gaps. The advances in silicon based devices have been significant in both the resolution of projection aligners and the etching of fine lines and spaces; however, where there is a need to fabricate a CCD with pixels having a dimension typically 6 .mu.m.times.6 .mu.m with two or more gates per pixel, it necessitates fabricating narrow CCD gates having a width in the order of 2.65 .mu.m and gaps in the order of 0.35 .mu.m while still achieving a high yield. To date, this task presents formidable problems to the fabricator.